Re: [PATCH v5 3/4] RISC-V: Remove CLINT related code from timer and arch

On 23/07/2020 16:24, Anup Patel wrote: > Right now the RISC-V timer driver is convoluted to support: > 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for >clocksource and SBI timer calls for clockevent device. > 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO >

[PATCH v5 3/4] RISC-V: Remove CLINT related code from timer and arch

Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT