Re: [PATCH v5 3/5] clk: aspeed: Add platform driver and register PLLs

On Mon, 2017-10-30 at 16:32 +1030, Joel Stanley wrote: > This registers a platform driver to set up all of the non-core > clocks. > > The clocks that have configurable rates are now registered. > > Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery > -- > v5: > - Remove eclk configurati

[PATCH v5 3/5] clk: aspeed: Add platform driver and register PLLs

This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley -- v5: - Remove eclk configuration. We do not have enough information to correctly implement the mux and divisor, so it will have to be