On Thursday, May 01, 2014 7:06 PM, Christoffer Dall wrote:
> On Thu, May 01, 2014 at 11:34:05AM +0900, Jungseok Lee wrote:
> > This patch adds memory layout and translation lookup information about
> > 48-bit address space with 4K pages. The description is based on 4
> > levels of translation
On Thu, May 01, 2014 at 11:34:05AM +0900, Jungseok Lee wrote:
> This patch adds memory layout and translation lookup information
> about 48-bit address space with 4K pages. The description is based
> on 4 levels of translation tables.
>
> Cc: Catalin Marinas
> Cc: Steve Capper
> Signed-off-by:
On Thu, May 01, 2014 at 11:34:05AM +0900, Jungseok Lee wrote:
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper
On Thursday, May 01, 2014 7:06 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:34:05AM +0900, Jungseok Lee wrote:
This patch adds memory layout and translation lookup information about
48-bit address space with 4K pages. The description is based on 4
levels of translation tables.
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas
Cc: Steve Capper
Signed-off-by: Jungseok Lee
Reviewed-by: Sungjinn Chung
---
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee
6 matches
Mail list logo