On 2021-03-17 10:02, Quentin Perret wrote:
On Wednesday 17 Mar 2021 at 09:41:09 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 18:46, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53:
On Wednesday 17 Mar 2021 at 09:41:09 (+0100), Mate Toth-Pal wrote:
> On 2021-03-16 18:46, Quentin Perret wrote:
> > On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
> > > On 2021-03-16 15:29, Quentin Perret wrote:
> > > > On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wr
On 2021-03-16 18:46, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
Changing th
On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
> On 2021-03-16 15:29, Quentin Perret wrote:
> > On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
> > > On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
> > > > Changing the value of MT_S2_FWB_NORMAL t
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
Changing the value of MT_S2_FWB_NORMAL to 7 would change this behavior, and
the resulting memory type would be device.
On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
> On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
> > Changing the value of MT_S2_FWB_NORMAL to 7 would change this behavior, and
> > the resulting memory type would be device.
>
> Sounds like the correct fix here -
On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
> Testing the latest version of the patchset, we seem to have found another
> thing related to FEAT_S2FWB.
Argh! I wish I could put my hands on hardware with FWB. Thanks again for
the report.
> This function always sets Normal memor
On 2021-03-15 15:35, Quentin Perret wrote:
+static int host_stage2_idmap(u64 addr)
+{
+ enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R | KVM_PGTABLE_PROT_W;
+ struct kvm_mem_range range;
+ bool is_memory = find_mem_range(addr, &range);
+ struct hyp_pool *pool = is_memory
When KVM runs in protected nVHE mode, make use of a stage 2 page-table
to give the hypervisor some control over the host memory accesses. The
host stage 2 is created lazily using large block mappings if possible,
and will default to page mappings in absence of a better solution.
>From this point o
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