Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-10-18 Thread Zhangshaokun
Hi Mark, On 2017/10/17 23:18, Mark Rutland wrote: > On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote: >> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon >> SoC. This patch adds support for HHA PMU driver, Each HHA has own >> control, counter and interrupt regis

Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-10-17 Thread Mark Rutland
On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote: > L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon > SoC. This patch adds support for HHA PMU driver, Each HHA has own > control, counter and interrupt registers and is an separate PMU. For > each HHA PMU, it has

[PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

2017-08-22 Thread Shaokun Zhang
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon SoC. This patch adds support for HHA PMU driver, Each HHA has own control, counter and interrupt registers and is an separate PMU. For each HHA PMU, it has 16-programable counters and each counter is free-running. Interrupt is