Re: [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver

2017-10-18 Thread Zhangshaokun
Hi Mark, On 2017/10/17 23:21, Mark Rutland wrote: > On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote: >> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each >> DDRC has own control, counter and interrupt registers and is an separate >> PMU. For each DDRC PMU, it ha

Re: [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver

2017-10-17 Thread Mark Rutland
On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote: > This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each > DDRC has own control, counter and interrupt registers and is an separate > PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been > mapped to 8

[PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver

2017-08-22 Thread Shaokun Zhang
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each DDRC has own control, counter and interrupt registers and is an separate PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been mapped to 8-events by hardware, it assumes that counter index is equal to event co