On Wed, 2015-07-22 at 10:27 +0530, Vinod Koul wrote:
> On Tue, Jul 21, 2015 at 10:08:28AM +0300, Andy Shevchenko wrote:
> > On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul
> > wrote:
> > > On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
> > > > > > +static void
On Wed, 2015-07-22 at 10:27 +0530, Vinod Koul wrote:
On Tue, Jul 21, 2015 at 10:08:28AM +0300, Andy Shevchenko wrote:
On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul vinod.k...@intel.com
wrote:
On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
+static void
On Tue, Jul 21, 2015 at 10:08:28AM +0300, Andy Shevchenko wrote:
> On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul wrote:
> > On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
> >> >> +static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
> >> >> *idma64c)
> >> >> +{
On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul wrote:
> On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
>> >> +static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
>> >> *idma64c)
>> >> +{
>> >> + u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
On Tue, Jul 21, 2015 at 10:08:28AM +0300, Andy Shevchenko wrote:
On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
*idma64c)
On Tue, Jul 21, 2015 at 7:50 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
*idma64c)
+{
+ u32 cfghi = IDMA64C_CFGH_SRC_PER(1) |
On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
> >> +static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
> >> *idma64c)
> >> +{
> >> + u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
> >> + u32 cfglo = 0;
> >> +
> >> + /* Enforce
On Fri, Jul 17, 2015 at 7:38 AM, Vinod Koul wrote:
> On Mon, Jul 06, 2015 at 03:22:13PM +0300, Andy Shevchenko wrote:
>> +config IDMA64
>> + tristate "Intel integrated DMA 64-bit support"
>> + select DMA_ENGINE
>> + select DMA_VIRTUAL_CHANNELS
> no help text?
Will fix.
>
>> +static
On Fri, Jul 17, 2015 at 7:38 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 06, 2015 at 03:22:13PM +0300, Andy Shevchenko wrote:
+config IDMA64
+ tristate Intel integrated DMA 64-bit support
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
no help text?
Will fix.
On Mon, Jul 20, 2015 at 11:46:28AM +0300, Andy Shevchenko wrote:
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
*idma64c)
+{
+ u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
+ u32 cfglo = 0;
+
+ /* Enforce FIFO drain when channel
On Mon, Jul 06, 2015 at 03:22:13PM +0300, Andy Shevchenko wrote:
> +config IDMA64
> + tristate "Intel integrated DMA 64-bit support"
> + select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
no help text?
> +static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
>
On Mon, Jul 06, 2015 at 03:22:13PM +0300, Andy Shevchenko wrote:
+config IDMA64
+ tristate Intel integrated DMA 64-bit support
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
no help text?
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan
*idma64c)
+{
Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
usage on each host controller independently.
While it has similarities with Synopsys DesignWare DMA, the following
distinctions doesn't allow to
Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
usage on each host controller independently.
While it has similarities with Synopsys DesignWare DMA, the following
distinctions doesn't allow to
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