On Tue, 15 Sep 2020, Xu Yilun wrote:
> This patch implements the basic functions of the BMC chip for some Intel
> FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
> Intel MAX 10 CPLD.
>
> This BMC chip is connected to the FPGA by a SPI bus. To provide direct
> register access
This patch implements the basic functions of the BMC chip for some Intel
FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
Intel MAX 10 CPLD.
This BMC chip is connected to the FPGA by a SPI bus. To provide direct
register access from the FPGA, the "SPI slave to Avalon Master Bri
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