On 04/06/2015 06:39 PM, Mark Brown wrote:> On Mon, Apr 06, 2015 at
03:54:23AM +0200, Bert Vermeulen wrote:
>> +if (spi->chip_select == 1 && t->cs_change) {
>> +/* CPLD in bulk write mode gets two bits per clock */
>> +do_spi_byte_fast(rbspi,
On 04/06/2015 06:39 PM, Mark Brown wrote: On Mon, Apr 06, 2015 at
03:54:23AM +0200, Bert Vermeulen wrote:
+if (spi-chip_select == 1 t-cs_change) {
+/* CPLD in bulk write mode gets two bits per clock */
+do_spi_byte_fast(rbspi, spi_ioc, out);
On Mon, Apr 06, 2015 at 03:54:23AM +0200, Bert Vermeulen wrote:
> + for (i = 0; i < t->len; ++i) {
> + out = tx_buf ? tx_buf[i] : 0x00;
This looks like the driver needs to set SPI_MASTER_MUST_TX.
> +/* Deselect CS0 and CS1. */
> +static int
On Mon, Apr 6, 2015 at 4:54 AM, Bert Vermeulen wrote:
> This driver mediates access between the connected CPLD and other devices
> on the bus.
>
> The m25p80-compatible boot flash and (some models) MMC use regular SPI,
> bitbanged as required by the SoC. However the SPI-connected CPLD has
> a
On Mon, Apr 6, 2015 at 4:54 AM, Bert Vermeulen b...@biot.com wrote:
This driver mediates access between the connected CPLD and other devices
on the bus.
The m25p80-compatible boot flash and (some models) MMC use regular SPI,
bitbanged as required by the SoC. However the SPI-connected CPLD has
On Mon, Apr 06, 2015 at 03:54:23AM +0200, Bert Vermeulen wrote:
+ for (i = 0; i t-len; ++i) {
+ out = tx_buf ? tx_buf[i] : 0x00;
This looks like the driver needs to set SPI_MASTER_MUST_TX.
+/* Deselect CS0 and CS1. */
+static int rb4xx_unprepare_transfer_hardware(struct
This driver mediates access between the connected CPLD and other devices
on the bus.
The m25p80-compatible boot flash and (some models) MMC use regular SPI,
bitbanged as required by the SoC. However the SPI-connected CPLD has
a "fast write" mode, in which two bits are transferred by SPI clock
This driver mediates access between the connected CPLD and other devices
on the bus.
The m25p80-compatible boot flash and (some models) MMC use regular SPI,
bitbanged as required by the SoC. However the SPI-connected CPLD has
a fast write mode, in which two bits are transferred by SPI clock
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