On Fri, May 29, 2020 at 03:22:26PM -0600, Rob Herring wrote:
> On Fri, May 29, 2020 at 06:33:25PM +0100, Mark Brown wrote:
> > Please rebase. TBH I'd not noticed Rob's review so I just left it
> > waiting for that, there's such a huge backlog there it didn't occur to
> > me that it might've been
On Fri, May 29, 2020 at 06:33:25PM +0100, Mark Brown wrote:
> On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
>
> > You must have missed the patch 16:
> > 0e8332aaf059 dt-bindings: spi: Convert DW SPI binding to DT schema
> > As you can see it has been acked by Rob. So you can also me
On Fri, May 29, 2020 at 08:43:12PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 06:18:32PM +0100, Mark Brown wrote:
> > > On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> > > > Baikal-T1 SoC provides a DW DMA contro
On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
> On Fri, May 29, 2020 at 06:18:32PM +0100, Mark Brown wrote:
> > On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> > > Baikal-T1 SoC provides a DW DMA controller to perform low-speed
> > > peripherals
> > > Mem-to-Dev and Dev-to-
Mark
On Fri, May 29, 2020 at 06:18:32PM +0100, Mark Brown wrote:
> On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices
On Fri, May 29, 2020 at 06:33:25PM +0100, Mark Brown wrote:
> On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
>
> > You must have missed the patch 16:
> > 0e8332aaf059 dt-bindings: spi: Convert DW SPI binding to DT schema
> > As you can see it has been acked by Rob. So you can also me
On Fri, May 29, 2020 at 08:26:42PM +0300, Serge Semin wrote:
> You must have missed the patch 16:
> 0e8332aaf059 dt-bindings: spi: Convert DW SPI binding to DT schema
> As you can see it has been acked by Rob. So you can also merge it into your
> repo. Though It has to be rebased first due to the
On Fri, 29 May 2020 16:11:49 +0300, Serge Semin wrote:
> Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> are supported
On Fri, May 29, 2020 at 04:11:49PM +0300, Serge Semin wrote:
> Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
> Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> APB SSI devices embedded into the SoC. Currently the DMA-based transfers
> are supp
Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
APB SSI devices embedded into the SoC. Currently the DMA-based transfers
are supported by the DW APB SPI driver only as a middle layer code for
Intel
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