subject:"\[PATCH v6 02\/15\] clk\: tegra\: Don't enable PLLE HW sequencer at init"

Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

2021-02-10 Thread Stephen Boyd

Quoting JC Kuo (2021-01-19 00:55:33) > PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware > power sequencers' output to enable/disable PLLE. PLLE hardware power > sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers > are enabled. > > Signed-off-by: JC Kuo >

Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

2021-01-19 Thread Thierry Reding

On Tue, Jan 19, 2021 at 04:55:33PM +0800, JC Kuo wrote: > PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware > power sequencers' output to enable/disable PLLE. PLLE hardware power > sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers > are enabled. > >

[PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

2021-01-19 Thread JC Kuo

PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- v6: no change v5: