On Friday 02 February 2018 11:20 PM, David Lechner wrote:
> On 02/02/2018 12:20 AM, Sekhar Nori wrote:
>> On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
>>> +EMIFA clock source (ASYNC1)
>>> +---
>>> +Required properties:
>>> +- compatible: shall be "ti,da850-asyn
On 02/02/2018 12:20 AM, Sekhar Nori wrote:
On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
+EMIFA clock source (ASYNC1)
+---
+Required properties:
+- compatible: shall be "ti,da850-async1-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+
On Saturday 20 January 2018 10:43 PM, David Lechner wrote:
> +EMIFA clock source (ASYNC1)
> +---
> +Required properties:
> +- compatible: shall be "ti,da850-async1-clksrc".
> +- #clock-cells: from common clock binding; shall be set to 0.
> +- clocks: phandles to the parent c
On Sat, Jan 20, 2018 at 11:13:56AM -0600, David Lechner wrote:
> This adds a new binding for the clocks present in the CFGCHIP syscon
> registers in TI DA8XX SoCs.
>
> Signed-off-by: David Lechner
> ---
>
> v6 changes:
> - combine "dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks",
This adds a new binding for the clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs.
Signed-off-by: David Lechner
---
v6 changes:
- combine "dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks",
"dt-bindings: clock: Add binding for TI DA8XX CFGCHIP mux clocks" and
"dt-
5 matches
Mail list logo