On Thu, Aug 04, 2016 at 04:32:57PM +0200, Geert Uytterhoeven wrote:
> Hi Rich,
>
> On Thu, Aug 4, 2016 at 6:30 AM, Rich Felker wrote:
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-jcore-aic.c
>
> > +int __init aic_irq_of_init(struct device_node *node, struct device_node
> >
On Thu, Aug 04, 2016 at 04:32:57PM +0200, Geert Uytterhoeven wrote:
> Hi Rich,
>
> On Thu, Aug 4, 2016 at 6:30 AM, Rich Felker wrote:
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-jcore-aic.c
>
> > +int __init aic_irq_of_init(struct device_node *node, struct device_node
> > *parent)
> > +{
>
Hi Rich,
On Thu, Aug 4, 2016 at 6:30 AM, Rich Felker wrote:
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> +int __init aic_irq_of_init(struct device_node *node, struct device_node
> *parent)
> +{
> + unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
> + unsigned
Hi Rich,
On Thu, Aug 4, 2016 at 6:30 AM, Rich Felker wrote:
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> +int __init aic_irq_of_init(struct device_node *node, struct device_node
> *parent)
> +{
> + unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
> + unsigned dom_sz =
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities
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