On 1/20/2015 1:53 AM, Linus Walleij wrote:
> On Sat, Jan 17, 2015 at 1:11 AM, Ray Jui wrote:
>> On 1/16/2015 2:14 AM, Linus Walleij wrote:
>
>>> Some hardware designs put the software-controlled biasing
>>> resistors in the GPIO block electronically connected to the actual
>>> pins, so that
On Sat, Jan 17, 2015 at 1:11 AM, Ray Jui wrote:
> On 1/16/2015 2:14 AM, Linus Walleij wrote:
>> Some hardware designs put the software-controlled biasing
>> resistors in the GPIO block electronically connected to the actual
>> pins, so that e.g. the biasing will be available if some MMC or
>>
On Sat, Jan 17, 2015 at 1:11 AM, Ray Jui r...@broadcom.com wrote:
On 1/16/2015 2:14 AM, Linus Walleij wrote:
Some hardware designs put the software-controlled biasing
resistors in the GPIO block electronically connected to the actual
pins, so that e.g. the biasing will be available if some
On 1/20/2015 1:53 AM, Linus Walleij wrote:
On Sat, Jan 17, 2015 at 1:11 AM, Ray Jui r...@broadcom.com wrote:
On 1/16/2015 2:14 AM, Linus Walleij wrote:
Some hardware designs put the software-controlled biasing
resistors in the GPIO block electronically connected to the actual
pins, so
On 1/16/2015 2:14 AM, Linus Walleij wrote:
> On Tue, Jan 13, 2015 at 6:05 PM, Ray Jui wrote:
>> On 1/13/2015 12:53 AM, Linus Walleij wrote:
>>> On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui wrote:
>>>
+/* drive strength control for ASIU GPIO */
+#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET
On Tue, Jan 13, 2015 at 6:05 PM, Ray Jui wrote:
> On 1/13/2015 12:53 AM, Linus Walleij wrote:
>> On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui wrote:
>>
>>> +/* drive strength control for ASIU GPIO */
>>> +#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
>>> +
>>> +/* drive strength control for CCM
On 1/16/2015 2:14 AM, Linus Walleij wrote:
On Tue, Jan 13, 2015 at 6:05 PM, Ray Jui r...@broadcom.com wrote:
On 1/13/2015 12:53 AM, Linus Walleij wrote:
On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui r...@broadcom.com wrote:
+/* drive strength control for ASIU GPIO */
+#define
On Tue, Jan 13, 2015 at 6:05 PM, Ray Jui r...@broadcom.com wrote:
On 1/13/2015 12:53 AM, Linus Walleij wrote:
On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui r...@broadcom.com wrote:
+/* drive strength control for ASIU GPIO */
+#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
+
+/* drive strength
On 1/13/2015 12:53 AM, Linus Walleij wrote:
> On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui wrote:
>
>> This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
>> SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
>> chipCommonG GPIO controller, and 3) the ALWAYS-ON
On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui wrote:
> This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
> SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
> chipCommonG GPIO controller, and 3) the ALWAYS-ON GPIO controller
>
> Signed-off-by: Ray Jui
>
On 1/13/2015 12:53 AM, Linus Walleij wrote:
On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui r...@broadcom.com wrote:
This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
chipCommonG GPIO controller, and 3) the
On Tue, Dec 16, 2014 at 3:18 AM, Ray Jui r...@broadcom.com wrote:
This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
chipCommonG GPIO controller, and 3) the ALWAYS-ON GPIO controller
Signed-off-by: Ray
This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
chipCommonG GPIO controller, and 3) the ALWAYS-ON GPIO controller
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
drivers/gpio/Kconfig |
This GPIO driver supports all 3 GPIO controllers in the Broadcom Cygnus
SoC. The 3 GPIO controllers are 1) the ASIU GPIO controller, 2) the
chipCommonG GPIO controller, and 3) the ALWAYS-ON GPIO controller
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
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