Re: [PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch

On Fri, 24 Jul 2020 00:18:21 PDT (-0700), Anup Patel wrote: Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use

Re: [PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch

On Sat, Jul 25, 2020 at 10:46 AM Atish Patra wrote: > > On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote: > > > > Right now the RISC-V timer driver is convoluted to support: > > 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for > >clocksource and SBI timer calls for clockevent

Re: [PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch

On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote: > > Right now the RISC-V timer driver is convoluted to support: > 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for >clocksource and SBI timer calls for clockevent device. > 2. Linux RISC-V M-mode (without MMU) where it will use

[PATCH v6 3/4] RISC-V: Remove CLINT related code from timer and arch

Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO