Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

2020-11-05 Thread Ramuthevar, Vadivel MuruganX
Hi Linus, Thank you for the review comments... On 5/11/2020 3:11 pm, Linus Walleij wrote: On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX wrote: + ddata = of_device_get_match_data(dev); + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) { + if

Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

2020-11-04 Thread Linus Walleij
On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX wrote: > + ddata = of_device_get_match_data(dev); > + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) { > + if (of_property_read_u32(np, "num-chipselect", The standard SPI bindings in spi-controller.

[PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

2020-10-29 Thread Ramuthevar,Vadivel MuruganX
From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/spi/sp