Hi Geert,
On Wed, 23 May 2018 at 12:18, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> > On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> > wrote:
> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> >> wrote:
> >> > + #address-cells = <1>;
Hi Michel,
On Wed, May 23, 2018 at 11:20 AM, M P wrote:
> On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
> wrote:
>> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> wrote:
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > +
>> > + cpus {
>> > + #ad
Hi Geert,
On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven
wrote:
> Hi Michel,
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> wrote:
> > This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> > bone support.
> >
> > This currently only handles generic parts (gic, architected timer)
> >
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> p
On Tue, May 22, 2018 at 11:01:24AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinct
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g03
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