On 02/13/2015 12:42 AM, Thierry Reding wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP
On 02/13/2015 12:42 AM, Thierry Reding wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The
On Thu, Feb 12, 2015 at 11:42:44PM +0100, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> > From: Tuomas Tynkkynen
> >
> > The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> > and also provides
On 02/12/2015 03:54 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate
On 02/13/2015 12:42 AM, Thierry Reding wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP
On 02/12/2015 03:54 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well.
On 02/13/2015 12:42 AM, Thierry Reding wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The
On Thu, Feb 12, 2015 at 11:42:44PM +0100, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen
>
> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> and also provides automatic CPU rail voltage scaling as well. The DFLL
> is a separate IP block from the usual Tegra124
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen
>
> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> and also provides automatic CPU rail voltage scaling as well. The DFLL
> is a separate IP block from the usual Tegra124
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual
From: Tuomas Tynkkynen
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the
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