Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-15 Thread Tuomas Tynkkynen
On 02/13/2015 12:42 AM, Thierry Reding wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-15 Thread Tuomas Tynkkynen
On 02/13/2015 12:42 AM, Thierry Reding wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Peter De Schrijver
On Thu, Feb 12, 2015 at 11:42:44PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: > > From: Tuomas Tynkkynen > > > > The DFLL is the main clocksource for the fast CPU cluster on Tegra124 > > and also provides

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Mikko Perttunen
On 02/12/2015 03:54 PM, Peter De Schrijver wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Mikko Perttunen
On 02/13/2015 12:42 AM, Thierry Reding wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Mikko Perttunen
On 02/12/2015 03:54 PM, Peter De Schrijver wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well.

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Mikko Perttunen
On 02/13/2015 12:42 AM, Thierry Reding wrote: On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-13 Thread Peter De Schrijver
On Thu, Feb 12, 2015 at 11:42:44PM +0100, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-12 Thread Thierry Reding
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen > > The DFLL is the main clocksource for the fast CPU cluster on Tegra124 > and also provides automatic CPU rail voltage scaling as well. The DFLL > is a separate IP block from the usual Tegra124

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen > > The DFLL is the main clocksource for the fast CPU cluster on Tegra124 > and also provides automatic CPU rail voltage scaling as well. The DFLL > is a separate IP block from the usual Tegra124

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-12 Thread Thierry Reding
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual

Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual

[PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-01-08 Thread Mikko Perttunen
From: Tuomas Tynkkynen The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the device tree.

[PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

2015-01-08 Thread Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the