Re: [PATCH v7 03/16] clk: tegra: Add closed loop support for the DFLL

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:06PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen > > With closed loop support, the clock rate of the DFLL can be adjusted. > > The oscillator itself in the DFLL is a free-running oscillator whose > rate is directly determined the supply voltage. However,

Re: [PATCH v7 03/16] clk: tegra: Add closed loop support for the DFLL

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:06PM +0200, Mikko Perttunen wrote: From: Tuomas Tynkkynen ttynkky...@nvidia.com With closed loop support, the clock rate of the DFLL can be adjusted. The oscillator itself in the DFLL is a free-running oscillator whose rate is directly determined the supply

[PATCH v7 03/16] clk: tegra: Add closed loop support for the DFLL

2015-01-08 Thread Mikko Perttunen
From: Tuomas Tynkkynen With closed loop support, the clock rate of the DFLL can be adjusted. The oscillator itself in the DFLL is a free-running oscillator whose rate is directly determined the supply voltage. However, the DFLL module contains logic to compare the DFLL output rate to a fixed

[PATCH v7 03/16] clk: tegra: Add closed loop support for the DFLL

2015-01-08 Thread Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com With closed loop support, the clock rate of the DFLL can be adjusted. The oscillator itself in the DFLL is a free-running oscillator whose rate is directly determined the supply voltage. However, the DFLL module contains logic to compare the DFLL