Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-16 Thread Tao Xu
On 7/17/2019 9:17 AM, Tao Xu wrote: On 7/17/2019 12:03 AM, Eduardo Habkost wrote: On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in

Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-16 Thread Tao Xu
On 7/17/2019 12:03 AM, Eduardo Habkost wrote: On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch emulates

Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-16 Thread Eduardo Habkost
On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: > UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H > to determines the maximum time in TSC-quanta that the processor can reside > in either C0.1 or C0.2. > > This patch emulates MSR IA32_UMWAIT_CONTROL in guest and

Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-15 Thread Sean Christopherson
On Mon, Jul 15, 2019 at 09:22:14AM +0800, Tao Xu wrote: > On 7/12/2019 11:52 PM, Sean Christopherson wrote: > >The SDM only defines bits 31:0, and the kernel uses a u32 to cache its > >value. I assume bits 63:32 are reserved? I'm guessing we also need an > >SDM update... > > > > The SDM define

Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-14 Thread Tao Xu
On 7/12/2019 11:52 PM, Sean Christopherson wrote: On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c index 6a204e7336c1..631152a67c6e 100644 --- a/arch/x86/kernel/cpu/umwait.c +++ b/arch/x86/kernel/cpu/umwait.c @@

Re: [PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-12 Thread Sean Christopherson
On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote: > diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c > index 6a204e7336c1..631152a67c6e 100644 > --- a/arch/x86/kernel/cpu/umwait.c > +++ b/arch/x86/kernel/cpu/umwait.c > @@ -15,7 +15,8 @@ > * Cache IA32_UMWAIT_CONTROL

[PATCH v7 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL

2019-07-12 Thread Tao Xu
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate IA32_UMWAIT_CONTROL between host and guest. The