Re: [PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-11-14 Thread Georgi Djakov
On 11/09/2016 08:24 PM, Rob Herring wrote: On Mon, Oct 31, 2016 at 04:55:26PM +0200, Georgi Djakov wrote: Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the

Re: [PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-11-14 Thread Georgi Djakov
On 11/09/2016 08:24 PM, Rob Herring wrote: On Mon, Oct 31, 2016 at 04:55:26PM +0200, Georgi Djakov wrote: Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the

Re: [PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-11-09 Thread Rob Herring
On Mon, Oct 31, 2016 at 04:55:26PM +0200, Georgi Djakov wrote: > Add a driver for the A53 Clock Controller. It is a hardware block that > implements a combined mux and half integer divider functionality. It can > choose between a fixed-rate clock or the dedicated A53 PLL. The source > and the

Re: [PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-11-09 Thread Rob Herring
On Mon, Oct 31, 2016 at 04:55:26PM +0200, Georgi Djakov wrote: > Add a driver for the A53 Clock Controller. It is a hardware block that > implements a combined mux and half integer divider functionality. It can > choose between a fixed-rate clock or the dedicated A53 PLL. The source > and the

[PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-10-31 Thread Georgi Djakov
Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated A53 PLL. The source and the divider can be set both at the same time. This is required for enabling

[PATCH v7 3/3] clk: qcom: Add A53 clock driver

2016-10-31 Thread Georgi Djakov
Add a driver for the A53 Clock Controller. It is a hardware block that implements a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated A53 PLL. The source and the divider can be set both at the same time. This is required for enabling