On Wed, Jul 20, 2016 at 3:15 AM, Will Deacon wrote:
> On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
>> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
>> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
>> >> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
>> >> > On
On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
> >> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
> >> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>
On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
> On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
>>
>> Hi Will,
>>
>> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
>> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>> >> In addition to the X-Gene ARM CPU performanc
On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
>
> Hi Will,
>
> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
> >> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
> >> are PMU for the SoC sys
Hi Will,
On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
> On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
>> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
>> memory controller b
On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
> memory controller bridges and memory. These PMU devices are loosely
> architected to fo
In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
memory controller bridges and memory. These PMU devices are loosely
architected to follow the same model as the PMU for ARM cores.
Signed-off-by: Tai Ng
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