[PATCH v8 09/18] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

From: Tuomas Tynkkynen The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen Signed-off-by: Mikko Perttunen --- drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++- 1 file changed, 3 insertions(+), 1

[PATCH v8 09/18] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi ---