Hi Laurent and Vinod,
On 24. 06. 20 23:14, Laurent Pinchart wrote:
> Hi Vinod,
>
> On Wed, Jun 24, 2020 at 10:56:35PM +0530, Vinod Koul wrote:
>> On 24-06-20, 19:39, Laurent Pinchart wrote:
>>
> +/* Number of GT lanes */
> +#define NUM_LANES4
Should this
Hi Vinod,
On Wed, Jun 24, 2020 at 10:56:35PM +0530, Vinod Koul wrote:
> On 24-06-20, 19:39, Laurent Pinchart wrote:
>
> > > > +/* Number of GT lanes */
> > > > +#define NUM_LANES 4
> > >
> > > Should this be coded in driver like this? Maybe future versions of
> > > hardware
Hi Laurent,
On 24-06-20, 19:39, Laurent Pinchart wrote:
> > > +/* Number of GT lanes */
> > > +#define NUM_LANES4
> >
> > Should this be coded in driver like this? Maybe future versions of
> > hardware will have more lanes..? Why not describe this in DT?
>
> This macro i
Hi Vinod,
On Wed, Jun 24, 2020 at 08:41:21PM +0530, Vinod Koul wrote:
> Hi Laurent,
>
> Mostly this looks fine to me, some minor nitpicks below:
>
> On 13-05-20, 20:22, Laurent Pinchart wrote:
> > +config PHY_XILINX_ZYNQMP
> > + tristate "Xilinx ZynqMP PHY driver"
> > + depends on ARCH_ZYNQM
Hi Laurent,
Mostly this looks fine to me, some minor nitpicks below:
On 13-05-20, 20:22, Laurent Pinchart wrote:
> +config PHY_XILINX_ZYNQMP
> + tristate "Xilinx ZynqMP PHY driver"
> + depends on ARCH_ZYNQMP
Can we add COMPILE_TEST here so that this driver gets wider compile
coverage?
>
From: Anurag Kumar Vulisha
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anu
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