Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-23 Thread Lorenzo Pieralisi
On Fri, Jun 23, 2017 at 06:55:41AM +0200, Robert Richter wrote: > On 22.06.17 22:04:37, Lorenzo Pieralisi wrote: > > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote: > > > On 22.06.17 19:58:22, Will Deacon wrote: > > > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: >

Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Robert Richter
On 22.06.17 22:04:37, Lorenzo Pieralisi wrote: > On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote: > > On 22.06.17 19:58:22, Will Deacon wrote: > > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > > > > On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: >

Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Lorenzo Pieralisi
On Thu, Jun 22, 2017 at 09:35:35PM +0200, Robert Richter wrote: > On 22.06.17 19:58:22, Will Deacon wrote: > > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > > > On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > > > > Cavium ThunderX2 SMMUv3 implementation has two S

Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Robert Richter
On 22.06.17 19:58:22, Will Deacon wrote: > On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > > On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > > > 1. Errata ID #74 > > >SMMU register alias Page

Re: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Will Deacon
On Thu, Jun 22, 2017 at 07:22:57PM +0100, Will Deacon wrote: > On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > > 1. Errata ID #74 > >SMMU register alias Page 1 is not implemented > > 2. Errata ID #126 > >

Re: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Will Deacon
On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >eventq

[PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-06-22 Thread Geetha sowjanya
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software workaround for these two