[PATCH v9 06/14] clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-pll.c |6 +++--- drivers/clk/tegra/clk-tegra20.c | 20 ++--

[PATCH v9 06/14] clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com --- drivers/clk/tegra/clk-pll.c |6 +++--- drivers/clk/tegra/clk-tegra20.c | 20