Quoting Paul Cercueil (2019-02-22 17:17:58)
> Bump.
>
> What should I do here?
>
I thought I replied to the list but maybe it got rejected because my MUA
is currently failing hard at sending 8-bit mails without
using quoted printable. Let me remove all non-ascii characters from this
mail!
If so
Hi,
Le jeu. 10 janv. 2019 à 11:04, Paul Cercueil a
écrit :
Adding Stephen to the discussion.
Adding Stephen to the discussion.
On Sat, Jan 5, 2019 at 6:27 PM, Uwe Kleine-König
wrote:
Hello Paul,
On Sat, Jan 05, 2019 at 06:05:38PM -0300, Paul Cercueil wrote:
On Sat, Jan 5, 2019 at 4:57 P
Adding Stephen to the discussion.
Adding Stephen to the discussion.
On Sat, Jan 5, 2019 at 6:27 PM, Uwe Kleine-König
wrote:
Hello Paul,
On Sat, Jan 05, 2019 at 06:05:38PM -0300, Paul Cercueil wrote:
On Sat, Jan 5, 2019 at 4:57 PM, Uwe Kleine-König
wrote:
> You are assuming stuff here abo
Hello Paul,
On Sat, Jan 05, 2019 at 06:05:38PM -0300, Paul Cercueil wrote:
> On Sat, Jan 5, 2019 at 4:57 PM, Uwe Kleine-König
> wrote:
> > You are assuming stuff here about the parent clk which isn't guaranteed
> > (AFAICT) by the clk framework: If you call clk_round_rate(clk, rate - 1)
> > this
Hi,
On Sat, Jan 5, 2019 at 4:57 PM, Uwe Kleine-König
wrote:
On Thu, Dec 27, 2018 at 07:13:06PM +0100, Paul Cercueil wrote:
The previous algorithm hardcoded details about how the TCU clocks
work.
The new algorithm will use clk_round_rate to find the perfect clock
rate
for the PWM channel.
On Thu, Dec 27, 2018 at 07:13:06PM +0100, Paul Cercueil wrote:
> The previous algorithm hardcoded details about how the TCU clocks work.
> The new algorithm will use clk_round_rate to find the perfect clock rate
> for the PWM channel.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Notes:
> v9:
The previous algorithm hardcoded details about how the TCU clocks work.
The new algorithm will use clk_round_rate to find the perfect clock rate
for the PWM channel.
Signed-off-by: Paul Cercueil
---
Notes:
v9: New patch
drivers/pwm/pwm-jz4740.c | 26 +++---
1 file chan
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