Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Brendan Higgins
>> + i2c_ic->irq_domain = irq_domain_add_linear( >> + node, ASPEED_I2C_IC_NUM_BUS, >> + _i2c_ic_irq_domain_ops, NULL); > > nit: can you have at least one argument following the function name? > Even if checkpatch shouts out you? Makes no difference to

Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Brendan Higgins
>> + i2c_ic->irq_domain = irq_domain_add_linear( >> + node, ASPEED_I2C_IC_NUM_BUS, >> + _i2c_ic_irq_domain_ops, NULL); > > nit: can you have at least one argument following the function name? > Even if checkpatch shouts out you? Makes no difference to

Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Marc Zyngier
On 02/06/17 09:46, Brendan Higgins wrote: > The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 > separate I2C busses. This adds a dummy irqchip which maps the single > hardware interrupt to software interrupts for each of the busses. > > Signed-off-by: Brendan Higgins

Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Marc Zyngier
On 02/06/17 09:46, Brendan Higgins wrote: > The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 > separate I2C busses. This adds a dummy irqchip which maps the single > hardware interrupt to software interrupts for each of the busses. > > Signed-off-by: Brendan Higgins > --- >

[PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Brendan Higgins
The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins --- Added in v6: - Pulled

[PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

2017-06-02 Thread Brendan Higgins
The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins --- Added in v6: - Pulled "aspeed_i2c_controller" out