[PATCH v9 3/5] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

[Ramuthevar,Vadivel MuruganX]

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthe...@linux.intel.com>

Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.

Signed-off-by: Ramuthevar Vadivel Murugan 
<vadivel.muruganx.ramuthe...@linux.intel.com>
---
 drivers/spi/spi-cadence-quadspi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c 
b/drivers/spi/spi-cadence-quadspi.c
index d12b765e87be..c7ecd6d44326 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -75,6 +75,7 @@ struct cqspi_st {
        bool                    is_decoded_cs;
        u32                     fifo_depth;
        u32                     fifo_width;
+       u32                     num_chipselect;
        bool                    rclk_en;
        u32                     trigger_address;
        u32                     wr_delay;
@@ -1070,6 +1071,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
                return -ENXIO;
        }
 
+       if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
+               cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
+
        cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
 
        return 0;
@@ -1302,6 +1306,8 @@ static int cqspi_probe(struct platform_device *pdev)
        cqspi->current_cs = -1;
        cqspi->sclk = 0;
 
+       master->num_chipselect = cqspi->num_chipselect;
+
        ret = cqspi_setup_flash(cqspi);
        if (ret) {
                dev_err(dev, "failed to setup flash parameters %d\n", ret);
-- 
2.11.0