Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

On 07/24, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > The debug base clock can be bypassed from the main PLL to the OSC1 clock. > The bypass register is the staysoc1(0x10) register that is in the clock > manager. > > This patch adds the option to get the correct parent for the

[PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen --- v2: remove