Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ran...@codeaurora.org>
Reviewed-by: Stephen Boyd <swb...@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 39cf0bee1eb0..3cc4c3e48b9b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -305,6 +305,13 @@ uart5: serial@994000 {
};
};
+ system-cache-controller@9200000 {
+ compatible = "qcom,sc7280-llcc";
+ reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0
0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
