On Tue, Mar 12, 2019 at 2:13 PM Thor Thayer wrote:
>
> Hi Rob,
>
> On 3/12/19 11:00 AM, Rob Herring wrote:
> > On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.tha...@linux.intel.com wrote:
> >> From: Thor Thayer
> >>
> >> Fix Stratix10 ECC bindings to specify only the single
> >> bit error. On
Hi Rob,
On 3/12/19 11:00 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Fix Stratix10 ECC bindings to specify only the single
> bit error. On Stratix10 double bit errors are handled
> as SErrors instead of interrupts.
> Indicate the differences between the ARM64 and
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
Indicate the differences between the ARM64 and ARM32
EDAC architecture in the bindings.
Signed-off-by: Thor Thayer
---
v2 No change
4 matches
Mail list logo
