Hi Mathieu,
On 6/26/2019 11:11 PM, Mathieu Poirier wrote:
Hi Sai,
On Sun, 23 Jun 2019 at 21:36, Sai Prakash Ranjan
wrote:
diff --git a/drivers/hwtracing/coresight/coresight-platform.c
b/drivers/hwtracing/coresight/coresight-platform.c
index 3c5ceda8db24..4990da2c13e9 100644
--- a/drivers/hwt
Hi Sai,
On Sun, 23 Jun 2019 at 21:36, Sai Prakash Ranjan
wrote:
>
> Coresight platform support assumes that a missing "cpu" phandle
> defaults to CPU0. This could be problematic and unnecessarily binds
> components to CPU0, where they may not be. Let us make the DT binding
> rules a bit stricter
On 6/24/2019 1:56 PM, Suzuki K Poulose wrote:
Sai,
Thanks for getting this done.
On 24/06/2019 04:36, Sai Prakash Ranjan wrote:
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may
Sai,
Thanks for getting this done.
On 24/06/2019 04:36, Sai Prakash Ranjan wrote:
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may not be. Let us make the DT binding
rules a bit
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may not be. Let us make the DT binding
rules a bit stricter by not defaulting to CPU0 for missing "cpu"
affinity information.
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