Re: [PATCHv3 8/8] x86/mm: Allow to have userspace mappings above 47-bits

2017-04-07 Thread Dmitry Safonov
On 04/07/2017 06:44 PM, Kirill A. Shutemov wrote: On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with

Re: [PATCHv3 8/8] x86/mm: Allow to have userspace mappings above 47-bits

2017-04-07 Thread Dmitry Safonov
On 04/07/2017 06:44 PM, Kirill A. Shutemov wrote: On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with

[PATCHv3 8/8] x86/mm: Allow to have userspace mappings above 47-bits

2017-04-07 Thread Kirill A. Shutemov
On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with valid pointers with 5-level paging and leads to

[PATCHv3 8/8] x86/mm: Allow to have userspace mappings above 47-bits

2017-04-07 Thread Kirill A. Shutemov
On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with valid pointers with 5-level paging and leads to