New version that adds better support for the A10 plus it fixes an
issue in the previous version.
Note that the A10 does not support the 24Mhz bypass mode.
--
Jon Smirl
jonsm...@gmail.com
pwm
Description: Binary data
I was unaware of this driver and reimplemented it. Patch is attached.
Some differences I noticed...
1) I implemented bypass mode
2) I had to do math in picoseconds to avoid round off/truncation errors.
3) counter registers are different lengths on SUN4 vs rest.
Can someone with a scope verify if
On 18/06/2014 at 01:26:06 +0200, Thierry Reding wrote :
> On Mon, May 19, 2014 at 08:10:02PM +0200, Alexandre Belloni wrote:
> > + /* By default, the polarity is inversed, set it to normal */
> > + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG,
> > +BIT_CH(PWM_ACT_STATE, 0) |
> >
On Mon, May 19, 2014 at 08:10:02PM +0200, Alexandre Belloni wrote:
[...]
> diff --git a/drivers/pwm/pwm-sunxi.c b/drivers/pwm/pwm-sunxi.c
[...]
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
These shoul
This adds a generic PWM framework driver for the PWM controller
found on Allwinner SoCs.
Signed-off-by: Alexandre Belloni
Acked-by: Maxime Ripard
---
drivers/pwm/Kconfig | 9 ++
drivers/pwm/Makefile| 1 +
drivers/pwm/pwm-sunxi.c | 338
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