; bhelg...@google.com;
> lorenzo.pieral...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; gustavo.pimen...@synopsys.com;
> Roy Zang ; jingooh...@gmail.com;
> andrew.mur...@arm.com; Mingkai Hu ; M.h. Lian
> ; Xiaowei Bao
> Subject: Re: [PATCHv7 04/12] PCI: designware-ep: Modify MSI an
-...@lists.ozlabs.org; bhelg...@google.com;
> lorenzo.pieral...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; gustavo.pimen...@synopsys.com;
> Roy Zang ; jingooh...@gmail.com;
> andrew.mur...@arm.com; Mingkai Hu ; M.h. Lian
> ; Xiaowei Bao
> Subject: Re: [PATCHv7 04/12] PCI:
On Tue, Aug 11, 2020 at 05:54:33PM +0800, Zhiqiang Hou wrote:
> From: Xiaowei Bao
>
> Each PF of EP device should have its own MSI or MSIX capabitily
> struct, so create a dw_pcie_ep_func struct and move the msi_cap
> and msix_cap to this struct from dw_pcie_ep, and manage the PFs
> via a list.
>
From: Xiaowei Bao
Each PF of EP device should have its own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and move the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
via a list.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase
4 matches
Mail list logo