Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Thor Thayer
On 01/22/2016 12:08 PM, Borislav Petkov wrote: On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote: it sounds like the author of the original change is Dinh, but if you agreed about authorship transfer, then "From: Thor Thayer" statement should be correct, but in any case your

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Borislav Petkov
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote: > it sounds like the author of the original change is Dinh, but if you agreed > about authorship transfer, then "From: Thor Thayer" statement should be > correct, but in any case your SoB should follow Dinh's SoB, if you decide to

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Vladimir Zapolskiy
Hi Thor, On 22.01.2016 17:35, Thor Thayer wrote: > Hi Vladimir, > > > On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote: >> Hi Thor, >> >> On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: >>> From: Thor Thayer >>> >>> Adding L2 Cache and On-Chip RAM EDAC support for the >>> Altera SoCs

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Thor Thayer
Hi Vladimir, On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote: Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Thor Thayer
Hi Vladimir, On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote: Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Borislav Petkov
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote: > it sounds like the author of the original change is Dinh, but if you agreed > about authorship transfer, then "From: Thor Thayer" statement should be > correct, but in any case your SoB should follow Dinh's SoB, if you decide to

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Thor Thayer
On 01/22/2016 12:08 PM, Borislav Petkov wrote: On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote: it sounds like the author of the original change is Dinh, but if you agreed about authorship transfer, then "From: Thor Thayer" statement should be correct, but in any case your

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-22 Thread Vladimir Zapolskiy
Hi Thor, On 22.01.2016 17:35, Thor Thayer wrote: > Hi Vladimir, > > > On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote: >> Hi Thor, >> >> On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: >>> From: Thor Thayer >>> >>> Adding L2 Cache and On-Chip RAM EDAC

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread Vladimir Zapolskiy
Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is individually

[PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- v8: Remove MASK

[PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer

Re: [PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-21 Thread Vladimir Zapolskiy
Hi Thor, On 21.01.2016 19:34, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type