On 01/22/2016 12:08 PM, Borislav Petkov wrote:
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
it sounds like the author of the original change is Dinh, but if you agreed
about authorship transfer, then "From: Thor Thayer" statement should be
correct, but in any case your
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
> it sounds like the author of the original change is Dinh, but if you agreed
> about authorship transfer, then "From: Thor Thayer" statement should be
> correct, but in any case your SoB should follow Dinh's SoB, if you decide to
Hi Thor,
On 22.01.2016 17:35, Thor Thayer wrote:
> Hi Vladimir,
>
>
> On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
>> Hi Thor,
>>
>> On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
>>> From: Thor Thayer
>>>
>>> Adding L2 Cache and On-Chip RAM EDAC support for the
>>> Altera SoCs
Hi Vladimir,
On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
Hi Vladimir,
On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
> it sounds like the author of the original change is Dinh, but if you agreed
> about authorship transfer, then "From: Thor Thayer" statement should be
> correct, but in any case your SoB should follow Dinh's SoB, if you decide to
On 01/22/2016 12:08 PM, Borislav Petkov wrote:
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
it sounds like the author of the original change is Dinh, but if you agreed
about authorship transfer, then "From: Thor Thayer" statement should be
correct, but in any case your
Hi Thor,
On 22.01.2016 17:35, Thor Thayer wrote:
> Hi Vladimir,
>
>
> On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
>> Hi Thor,
>>
>> On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
>>> From: Thor Thayer
>>>
>>> Adding L2 Cache and On-Chip RAM EDAC
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC device model. The SDRAM
> controller is using the Memory Controller model.
>
> Each type of ECC is individually
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer
Signed-off-by: Dinh Nguyen
---
v8: Remove MASK
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC device model. The SDRAM
> controller is using the Memory Controller model.
>
> Each type
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