On Wed, Oct 31, 2012 at 6:21 AM, Namhyung Kim wrote:
> On Mon, 29 Oct 2012 16:15:48 +0100, Stephane Eranian wrote:
>> This patch adds support for PEBS Precise Store
>> which is available on Intel Sandy Bridge and
>> Ivy Bridge processors.
>>
>> To use Precise store, the proper PEBS event
>> must b
On Mon, 29 Oct 2012 16:15:48 +0100, Stephane Eranian wrote:
> This patch adds support for PEBS Precise Store
> which is available on Intel Sandy Bridge and
> Ivy Bridge processors.
>
> To use Precise store, the proper PEBS event
> must be used: mem_trans_retired:precise_stores.
> For the perf tool,
On Mon, Oct 29, 2012 at 4:40 PM, Peter Zijlstra wrote:
> On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
>> - if (fll) {
>> + if (fll || fst) {
>> if (sample_type & PERF_SAMPLE_ADDR)
>> data.addr = pebs->dla;
>>
>> @@ -688,6 +731,8 @@
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> - if (fll) {
> + if (fll || fst) {
> if (sample_type & PERF_SAMPLE_ADDR)
> data.addr = pebs->dla;
>
> @@ -688,6 +731,8 @@ static void __intel_pmu_pebs_event(struct perf_event
> *event
This patch adds support for PEBS Precise Store
which is available on Intel Sandy Bridge and
Ivy Bridge processors.
To use Precise store, the proper PEBS event
must be used: mem_trans_retired:precise_stores.
For the perf tool, the generic mem-stores event
exported via sysfs can be used directly.
S
5 matches
Mail list logo