Re: [RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors

2017-10-05 Thread Philipp Zabel
On Wed, 2017-10-04 at 23:25 +0100, Bryan O'Donoghue wrote: > i.MX7S/D have a different scheme for addressing the OTP registers > inside > the OCOTP block. Currently it's possible to address the wrong OTP > registers > given the disparity between IMX6 and IMX7 OTP addressing. > > Since OTP

Re: [RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors

2017-10-05 Thread Philipp Zabel
On Wed, 2017-10-04 at 23:25 +0100, Bryan O'Donoghue wrote: > i.MX7S/D have a different scheme for addressing the OTP registers > inside > the OCOTP block. Currently it's possible to address the wrong OTP > registers > given the disparity between IMX6 and IMX7 OTP addressing. > > Since OTP

[RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors

2017-10-04 Thread Bryan O'Donoghue
i.MX7S/D have a different scheme for addressing the OTP registers inside the OCOTP block. Currently it's possible to address the wrong OTP registers given the disparity between IMX6 and IMX7 OTP addressing. Since OTP programming is one-time destructive its important we restrict this interface

[RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors

2017-10-04 Thread Bryan O'Donoghue
i.MX7S/D have a different scheme for addressing the OTP registers inside the OCOTP block. Currently it's possible to address the wrong OTP registers given the disparity between IMX6 and IMX7 OTP addressing. Since OTP programming is one-time destructive its important we restrict this interface