On Sat, Oct 12, 2019 at 4:12 AM Richard Zhu wrote:
>
> Hi Daniel:
> New version patch-set had been sent out on Oct9.
> https://patchwork.kernel.org/cover/11180683/
Thanks Richard. Jassi, care to have a look?
Daniel
> Daniel Baluta ; Aisheng Dong
> ; dl-linux-imx ; Linux Kernel
> Mailing List ; linux-arm-kernel
>
> Subject: RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for
> imx v1 mu
>
> Hi Daniel:
>
>
> > -Original Message-
> > From: Daniel Balut
: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1
> mu
>
>
> Hi Richard,
>
> Can you please rebase and resend this patch series?
>
[Richard Zhu] No problem, I would resend this patch-set later.
Best Regards
Richard Zhu
> On Mon, Aug 5, 2019 at
Hi Richard,
Can you please rebase and resend this patch series?
On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta wrote:
>
> On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu wrote:
> >
> > There is a version 1.0 MU on i.MX7ULP platform.
> > One new version ID register is added, and it's offset is 0.
> >
On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu wrote:
>
> There is a version 1.0 MU on i.MX7ULP platform.
> One new version ID register is added, and it's offset is 0.
> TRn registers are defined at the offset 0x20 ~ 0x2C.
> RRn registers are defined at the offset 0x40 ~ 0x4C.
> SR/CR registers are de
There is a version 1.0 MU on i.MX7ULP platform.
One new version ID register is added, and it's offset is 0.
TRn registers are defined at the offset 0x20 ~ 0x2C.
RRn registers are defined at the offset 0x40 ~ 0x4C.
SR/CR registers are defined at 0x60/0x64.
Extend this driver to support it.
Signed-o
6 matches
Mail list logo
