Re: [RESEND RFC 5/5] PCIe, AER: Update initial value of UC error mask

2014-09-09 Thread Chen, Gong
; Subject: Re: [RESEND RFC 5/5] PCIe, AER: Update initial value of UC error > mask > User-Agent: Mutt/1.5.21 (2010-09-15) > > On Wed, Aug 13, 2014 at 02:22:41AM -0400, Chen, Gong wrote: > > In PCI-e SPEC r3.0, BIT 0 of Uncorrectable Error Status Register > > is redefined

Re: [RESEND RFC 5/5] PCIe, AER: Update initial value of UC error mask

2014-09-05 Thread Bjorn Helgaas
On Wed, Aug 13, 2014 at 02:22:41AM -0400, Chen, Gong wrote: > In PCI-e SPEC r3.0, BIT 0 of Uncorrectable Error Status Register > is redefined and it has an explicit requirement that when writing > this field, a value of 1b is the only choice. So change previous > initial maks from 0 to 1. > > Sign

[RESEND RFC 5/5] PCIe, AER: Update initial value of UC error mask

2014-08-12 Thread Chen, Gong
In PCI-e SPEC r3.0, BIT 0 of Uncorrectable Error Status Register is redefined and it has an explicit requirement that when writing this field, a value of 1b is the only choice. So change previous initial maks from 0 to 1. Signed-off-by: Chen, Gong --- NOTE: After scratching all use cases, this is