On 28.6.2018 15:58, Michal Vokáč wrote:
On 25.6.2018 04:50, Andy Duan wrote:
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any
convenient way to configure the pad group control registers?
T
On 25.6.2018 04:50, Andy Duan wrote:
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any
convenient way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and O
ts.infradead.org; Shawn Guo
> > ; Sascha Hauer ;
> Fabio
> > Estevam ; Rob Herring
> ;
> > devicet...@vger.kernel.org; A.s. Dong ;
> Fabio
> > Estevam ; Shawn Guo ;
> Stefan
> > Agner ; Pengutronix Kernel Team
> > ; Linus Walleij ;
> > linux- k
; Rob Herring ;
> devicet...@vger.kernel.org; A.s. Dong ; Fabio
> Estevam ; Shawn Guo ;
> Stefan Agner ; Pengutronix Kernel Team
> ; Linus Walleij ; linux-
> ker...@vger.kernel.org
> Subject: Re: [RFC] Configure i.MX6 RGMII pad group control registers from
> device tree
>
&
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any convenient
way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and ODT) in the individual RGMII pad
contro
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