Hi Len,
On 15 August 2014 18:11, Len Brown wrote:
> The Linux team at Intel did not implement ACPI CPPC support
> because we see no benefit to it over the native hardware interface on x86.
>
Thanks for sharing Intels observations. I had looked at the SDM [1]
and found all the CPPC MSRs. I suppos
Hello,
On 15 August 2014 10:41, Peter Zijlstra wrote:
> On Fri, Aug 15, 2014 at 10:37:32AM -0400, Ashwin Chaugule wrote:
>> On 15 August 2014 10:07, Peter Zijlstra wrote:
>> > On Fri, Aug 15, 2014 at 09:08:50AM -0400, Ashwin Chaugule wrote:
>> >> If the OS only looks at Highest, Lowest, Delivere
> I verified that CPU freq requests were taken by reading out the PERF_STATUS
> register.
Don't use the x86 PERF_STATUS register -- it will not tell you what
you want to know.
If you want to see the actual frequency, you need to watch how many
cycles elapse per a known time interval,
which is ho
The Linux team at Intel did not implement ACPI CPPC support
because we see no benefit to it over the native hardware interface on x86.
cheers,
Len Brown
Intel Open Source Technology Center
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Hello,
On 15 August 2014 11:47, Arjan van de Ven wrote:
> On 8/15/2014 7:24 AM, Ashwin Chaugule wrote:
we've found that so far that there are two reasonable options
1) Let the OS device (old style)
2) Let the hardware decide (new style)
2) is there in practice today in th
On 8/15/2014 7:24 AM, Ashwin Chaugule wrote:
we've found that so far that there are two reasonable options
1) Let the OS device (old style)
2) Let the hardware decide (new style)
2) is there in practice today in the turbo range (which is increasingly
the whole thing)
and the hardware can make d
On Fri, Aug 15, 2014 at 10:37:32AM -0400, Ashwin Chaugule wrote:
> Hi Peter,
>
> On 15 August 2014 10:07, Peter Zijlstra wrote:
> > On Fri, Aug 15, 2014 at 09:08:50AM -0400, Ashwin Chaugule wrote:
> >> If the OS only looks at Highest, Lowest, Delivered registers and only
> >> writes to Desired, t
Hi Peter,
On 15 August 2014 10:07, Peter Zijlstra wrote:
> On Fri, Aug 15, 2014 at 09:08:50AM -0400, Ashwin Chaugule wrote:
>> If the OS only looks at Highest, Lowest, Delivered registers and only
>> writes to Desired, then we're not really any different than how we do
>> things today in the CPUF
Hi Arjan,
On 15 August 2014 09:53, Arjan van de Ven wrote:
> On 8/15/2014 6:42 AM, Arjan van de Ven wrote:
>> On 8/15/2014 6:08 AM, Ashwin Chaugule wrote:
>>> (b) we come up with ways to provide the bounds around a Desired value
>>> using the information from the platform. (long term)
>>>
>>> I b
On Fri, Aug 15, 2014 at 09:08:50AM -0400, Ashwin Chaugule wrote:
> If the OS only looks at Highest, Lowest, Delivered registers and only
> writes to Desired, then we're not really any different than how we do
> things today in the CPUFreq layer.
The thing is; we're already struggling to make 'sens
On Fri, Aug 15, 2014 at 06:42:51AM -0700, Arjan van de Ven wrote:
> On 8/15/2014 6:08 AM, Ashwin Chaugule wrote:
> >(b) we come up with ways to provide the bounds around a Desired value
> >using the information from the platform. (long term)
> >
> >I briefly looked at the x86 HWP (Hardware Performa
On 8/15/2014 6:42 AM, Arjan van de Ven wrote:
On 8/15/2014 6:08 AM, Ashwin Chaugule wrote:
(b) we come up with ways to provide the bounds around a Desired value
using the information from the platform. (long term)
I briefly looked at the x86 HWP (Hardware Performance States) in the
s/w manual a
On 8/15/2014 6:08 AM, Ashwin Chaugule wrote:
(b) we come up with ways to provide the bounds around a Desired value
using the information from the platform. (long term)
I briefly looked at the x86 HWP (Hardware Performance States) in the
s/w manual again. Its essentially an implementation of CPPC
Hi Peter,
On 15 August 2014 02:19, Peter Zijlstra wrote:
> On Thu, Aug 14, 2014 at 05:56:10PM -0400, Ashwin Chaugule wrote:
>> On 14 August 2014 16:51, Peter Zijlstra wrote:
>> > On Thu, Aug 14, 2014 at 03:57:07PM -0400, Ashwin Chaugule wrote:
>> >>
>> >>
>> >> What is CPPC:
>> >> =
On Thu, Aug 14, 2014 at 05:56:10PM -0400, Ashwin Chaugule wrote:
> Hi Peter,
>
> On 14 August 2014 16:51, Peter Zijlstra wrote:
> > On Thu, Aug 14, 2014 at 03:57:07PM -0400, Ashwin Chaugule wrote:
> >>
> >>
> >> What is CPPC:
> >> =
> >>
> >> CPPC is the new interface for CPU performa
Hi Peter,
On 14 August 2014 16:51, Peter Zijlstra wrote:
> On Thu, Aug 14, 2014 at 03:57:07PM -0400, Ashwin Chaugule wrote:
>>
>>
>> What is CPPC:
>> =
>>
>> CPPC is the new interface for CPU performance control between the OS and the
>> platform defined in ACPI 5.0+. The interface is
On Thu, Aug 14, 2014 at 03:57:07PM -0400, Ashwin Chaugule wrote:
>
>
> What is CPPC:
> =
>
> CPPC is the new interface for CPU performance control between the OS and the
> platform defined in ACPI 5.0+. The interface is built on an abstract
> representation of CPU performance rather
+ Rafael [corrected email addr]
On 14 August 2014 15:57, Ashwin Chaugule wrote:
>
> Hello,
>
> Apologies in advance for a lengthy cover letter. Hopefully it has all the
> required information so you dont need to read the ACPI spec. ;)
>
> This patchset introduces the ideas behind CPPC (Collabora
Hello,
Apologies in advance for a lengthy cover letter. Hopefully it has all the
required information so you dont need to read the ACPI spec. ;)
This patchset introduces the ideas behind CPPC (Collaborative Processor
Performance Control) and implements support for controlling CPU performance
usi
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