On Wed, May 25, 2016 at 7:22 AM, Andrew Jeffery wrote:
> [Me]
>> > +#define A4 2
>> > +SSSF_PIN_DECL(A4, GPIOA2, TIMER3, FUNC_DESC_SET(SCU80, 2));
>> > +
>> > +FUNC_EXPR_DECL_SINGLE(SD1, FUNC_DESC_SET(SCU90, 0));
>> > +
>> > +FUNC_EXPR_DECL_SINGLE(I2C10, FUNC_DESC_SET(SCU90, 23));
>> > +
>> > +#de
Hi Linus,
On Mon, 2016-05-23 at 14:38 +0200, Linus Walleij wrote:
> Hi sorry for taking so long before reviewing. Too busy, what can I say.
No worries, I expected as much. Thanks for taking the time!
>
> On Fri, May 6, 2016 at 8:20 AM, Andrew Jeffery wrote:
>
> >
> > Add pinctrl/pinmux suppo
Hi sorry for taking so long before reviewing. Too busy, what can I say.
On Fri, May 6, 2016 at 8:20 AM, Andrew Jeffery wrote:
> Add pinctrl/pinmux support for the Aspeed AST2400 SoC. Configuration of
> the SoC is somewhat involved: Enabling functions can involve writes of
> multiple bits to mult
Hi all,
This is a patch partially implementing a pinctrl/pinmux driver for the Aspeed
AST2400 ARM SoC, complementing Joel Stanley's recent series[1] adding the core
support for the chip. With additional integration patches there's enough pinmux
to boot the SoC and configure a number of i2c busses,
Add pinctrl/pinmux support for the Aspeed AST2400 SoC. Configuration of
the SoC is somewhat involved: Enabling functions can involve writes of
multiple bits to multiple registers, and signals provided by a pin are
determined on a priority basis. That is, without care, it's possible to
configure a f
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