Hi Peter
On 1/25/21 10:25 AM, Peter Zijlstra wrote:
On Fri, Jan 22, 2021 at 03:18:29PM +, Suzuki K Poulose wrote:
CoreSight PMU supports aux-buffer for the ETM tracing. The trace
generated by the ETM (associated with individual CPUs, like Intel PT)
is captured by a separate IP (CoreSight TM
On Mon, Jan 25, 2021 at 10:45:06AM +, Suzuki K Poulose wrote:
> On 1/25/21 10:25 AM, Peter Zijlstra wrote:
> > Since we have a whole u64, do we want to reserve a whole nibble (or
> > maybe even a byte) for a format type? Because with a single bit like
> > this, we'll kick ourselves when we end
On Fri, Jan 22, 2021 at 03:18:29PM +, Suzuki K Poulose wrote:
> CoreSight PMU supports aux-buffer for the ETM tracing. The trace
> generated by the ETM (associated with individual CPUs, like Intel PT)
> is captured by a separate IP (CoreSight TMC-ETR/ETF until now).
>
> The TMC-ETR applies for
CoreSight PMU supports aux-buffer for the ETM tracing. The trace
generated by the ETM (associated with individual CPUs, like Intel PT)
is captured by a separate IP (CoreSight TMC-ETR/ETF until now).
The TMC-ETR applies formatting of the raw ETM trace data, as it
can collect traces from multiple ET
4 matches
Mail list logo