On 10/03/2017 10:31, Yu Zhang wrote:
>> We can also add a module parameter to force emulation, so that it will
>> be possible to test UMIP emulation on newer processors too.
>
> Thanks for your reply, Paolo. :-)
>
> Well, my previous understanding is that there might be a situation on a
>
On 10/03/2017 10:31, Yu Zhang wrote:
>> We can also add a module parameter to force emulation, so that it will
>> be possible to test UMIP emulation on newer processors too.
>
> Thanks for your reply, Paolo. :-)
>
> Well, my previous understanding is that there might be a situation on a
>
On 3/10/2017 5:31 PM, Yu Zhang wrote:
On 3/10/2017 4:36 PM, Paolo Bonzini wrote:
On 10/03/2017 09:02, Yu Zhang wrote:
Besides, is this all the test for UMIP unit test? I.e. do we
need to
construct a scenario in the test to trigger vm exit and let hypervisor
inject a GP fault? - I did
On 3/10/2017 5:31 PM, Yu Zhang wrote:
On 3/10/2017 4:36 PM, Paolo Bonzini wrote:
On 10/03/2017 09:02, Yu Zhang wrote:
Besides, is this all the test for UMIP unit test? I.e. do we
need to
construct a scenario in the test to trigger vm exit and let hypervisor
inject a GP fault? - I did
On 3/10/2017 4:36 PM, Paolo Bonzini wrote:
On 10/03/2017 09:02, Yu Zhang wrote:
Besides, is this all the test for UMIP unit test? I.e. do we need to
construct a scenario in the test to trigger vm exit and let hypervisor
inject a GP fault? - I did not see this scenario in this patch. Or
On 3/10/2017 4:36 PM, Paolo Bonzini wrote:
On 10/03/2017 09:02, Yu Zhang wrote:
Besides, is this all the test for UMIP unit test? I.e. do we need to
construct a scenario in the test to trigger vm exit and let hypervisor
inject a GP fault? - I did not see this scenario in this patch. Or
On 10/03/2017 09:02, Yu Zhang wrote:
>> Besides, is this all the test for UMIP unit test? I.e. do we need to
>> construct a scenario in the test to trigger vm exit and let hypervisor
>> inject a GP fault? - I did not see this scenario in this patch. Or any
>> other suggestions? :-)
>
> Hi
On 10/03/2017 09:02, Yu Zhang wrote:
>> Besides, is this all the test for UMIP unit test? I.e. do we need to
>> construct a scenario in the test to trigger vm exit and let hypervisor
>> inject a GP fault? - I did not see this scenario in this patch. Or any
>> other suggestions? :-)
>
> Hi
On 3/1/2017 5:04 PM, Yu Zhang wrote:
On 12/13/2016 7:03 PM, Paolo Bonzini wrote:
On 13/12/2016 05:03, Li, Liang Z wrote:
Hi Paolo,
We intended to enable UMIP for KVM and found you had already worked
on it.
Do you have any plan for the following patch set? It's there
anything else you
On 3/1/2017 5:04 PM, Yu Zhang wrote:
On 12/13/2016 7:03 PM, Paolo Bonzini wrote:
On 13/12/2016 05:03, Li, Liang Z wrote:
Hi Paolo,
We intended to enable UMIP for KVM and found you had already worked
on it.
Do you have any plan for the following patch set? It's there
anything else you
nesday, March 1, 2017 10:04:17 AM
> Subject: Re: [RFC PATCH 0/4] KVM: Emulate UMIP (or almost do so)
>
>
>
> On 12/13/2016 7:03 PM, Paolo Bonzini wrote:
> >
> > On 13/12/2016 05:03, Li, Liang Z wrote:
> >> Hi Paolo,
> >>
> >> We intended to en
- Original Message -
> From: "Yu Zhang"
> To: "Paolo Bonzini"
> Cc: "qian ouyang" , linux-kernel@vger.kernel.org,
> k...@vger.kernel.org
> Sent: Wednesday, March 1, 2017 10:04:17 AM
> Subject: Re: [RFC PATCH 0/4] KVM: Emulate UMIP (o
On 12/13/2016 7:03 PM, Paolo Bonzini wrote:
On 13/12/2016 05:03, Li, Liang Z wrote:
Hi Paolo,
We intended to enable UMIP for KVM and found you had already worked on it.
Do you have any plan for the following patch set? It's there anything else you
expect
us help to do?
Yes, I plan to
On 12/13/2016 7:03 PM, Paolo Bonzini wrote:
On 13/12/2016 05:03, Li, Liang Z wrote:
Hi Paolo,
We intended to enable UMIP for KVM and found you had already worked on it.
Do you have any plan for the following patch set? It's there anything else you
expect
us help to do?
Yes, I plan to
On 13/12/2016 05:03, Li, Liang Z wrote:
> Hi Paolo,
>
> We intended to enable UMIP for KVM and found you had already worked on it.
> Do you have any plan for the following patch set? It's there anything else
> you expect
> us help to do?
Yes, I plan to resend these patches for 4.11.
Paolo
On 13/12/2016 05:03, Li, Liang Z wrote:
> Hi Paolo,
>
> We intended to enable UMIP for KVM and found you had already worked on it.
> Do you have any plan for the following patch set? It's there anything else
> you expect
> us help to do?
Yes, I plan to resend these patches for 4.11.
Paolo
> UMIP (User-Mode Instruction Prevention) is a feature of future Intel
> processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT and SMSW from
> user-mode processes.
>
> The idea here is to use virtualization intercepts to emulate UMIP; it slows
> down the instructions when they're executed in
> UMIP (User-Mode Instruction Prevention) is a feature of future Intel
> processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT and SMSW from
> user-mode processes.
>
> The idea here is to use virtualization intercepts to emulate UMIP; it slows
> down the instructions when they're executed in
On 13/07/2016 10:29, Yang Zhang wrote:
> On 2016/7/13 3:20, Paolo Bonzini wrote:
>> UMIP (User-Mode Instruction Prevention) is a feature of future
>> Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
>
> I remember there is no Cannonlake any more. It should be Icelake. :)
>
>>
On 13/07/2016 10:29, Yang Zhang wrote:
> On 2016/7/13 3:20, Paolo Bonzini wrote:
>> UMIP (User-Mode Instruction Prevention) is a feature of future
>> Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
>
> I remember there is no Cannonlake any more. It should be Icelake. :)
>
>>
On 2016/7/13 3:20, Paolo Bonzini wrote:
UMIP (User-Mode Instruction Prevention) is a feature of future
Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
I remember there is no Cannonlake any more. It should be Icelake. :)
and SMSW from user-mode processes.
Do you know the
On 2016/7/13 3:20, Paolo Bonzini wrote:
UMIP (User-Mode Instruction Prevention) is a feature of future
Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
I remember there is no Cannonlake any more. It should be Icelake. :)
and SMSW from user-mode processes.
Do you know the
UMIP (User-Mode Instruction Prevention) is a feature of future
Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
and SMSW from user-mode processes.
The idea here is to use virtualization intercepts to emulate UMIP; it
slows down the instructions when they're executed in ring 0, but
UMIP (User-Mode Instruction Prevention) is a feature of future
Intel processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT
and SMSW from user-mode processes.
The idea here is to use virtualization intercepts to emulate UMIP; it
slows down the instructions when they're executed in ring 0, but
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