> What's your suggestions? a new zone or a new migratetype?
> Maybe add a new zone will change more mm code.
I don't understand this code well enough (yet) to make a recommendation. I
think
our primary concern may not be "how much code we change", but more "how can
we minimize the run-time impac
On 2015/6/19 4:33, Luck, Tony wrote:
> On Thu, Jun 18, 2015 at 11:55:42AM +0200, Vlastimil Babka wrote:
> If there are many mirror regions in one node, then it will be many holes
> in the
> normal zone, is this fine?
Yeah, it doesn't matter how many holes there are.
>>>
>>>
On Thu, Jun 18, 2015 at 11:55:42AM +0200, Vlastimil Babka wrote:
> >>>If there are many mirror regions in one node, then it will be many holes
> >>>in the
> >>>normal zone, is this fine?
> >>
> >>Yeah, it doesn't matter how many holes there are.
> >
> >So mirror zone and normal zone will span each
On 06/18/2015 11:37 AM, Xishi Qiu wrote:
On 2015/6/18 13:58, Vlastimil Babka wrote:
On 18.6.2015 3:23, Xishi Qiu wrote:
On 2015/6/16 17:46, Vlastimil Babka wrote:
On the other hand, it would skip just as inefficiently over MIGRATE_MIRROR
pageblocks within a Normal zone. Since migrating page
On 2015/6/18 13:58, Vlastimil Babka wrote:
> On 18.6.2015 3:23, Xishi Qiu wrote:
>> On 2015/6/16 17:46, Vlastimil Babka wrote:
>>
>>> On 06/16/2015 10:17 AM, Xishi Qiu wrote:
On 2015/6/16 15:53, Vlastimil Babka wrote:
> On 06/04/2015 02:54 PM, Xishi Qiu wrote:
>>
>> I think a
On 18.6.2015 3:23, Xishi Qiu wrote:
> On 2015/6/16 17:46, Vlastimil Babka wrote:
>
>> On 06/16/2015 10:17 AM, Xishi Qiu wrote:
>>> On 2015/6/16 15:53, Vlastimil Babka wrote:
>>>
On 06/04/2015 02:54 PM, Xishi Qiu wrote:
>
> I think add a new migratetype is btter and easier than a new z
On 2015/6/16 17:46, Vlastimil Babka wrote:
> On 06/16/2015 10:17 AM, Xishi Qiu wrote:
>> On 2015/6/16 15:53, Vlastimil Babka wrote:
>>
>>> On 06/04/2015 02:54 PM, Xishi Qiu wrote:
I think add a new migratetype is btter and easier than a new zone, so I use
>>>
>>> If the mirrored memory i
On 06/16/2015 10:17 AM, Xishi Qiu wrote:
> On 2015/6/16 15:53, Vlastimil Babka wrote:
>
>> On 06/04/2015 02:54 PM, Xishi Qiu wrote:
>>>
>>> I think add a new migratetype is btter and easier than a new zone, so I use
>>
>> If the mirrored memory is in a single reasonably compact (no large holes)
On 2015/6/16 15:53, Vlastimil Babka wrote:
> On 06/04/2015 02:54 PM, Xishi Qiu wrote:
>> Intel Xeon processor E7 v3 product family-based platforms introduces support
>> for partial memory mirroring called as 'Address Range Mirroring'. This
>> feature
>> allows BIOS to specify a subset of total av
On 06/04/2015 02:54 PM, Xishi Qiu wrote:
> Intel Xeon processor E7 v3 product family-based platforms introduces support
> for partial memory mirroring called as 'Address Range Mirroring'. This feature
> allows BIOS to specify a subset of total available memory to be mirrored (and
> optionally also
On Fri, Jun 12, 2015 at 12:03:35PM -0700, Luck, Tony wrote:
> On Fri, Jun 12, 2015 at 08:42:33AM +, Naoya Horiguchi wrote:
> > 4?) I don't have the whole picture of how address ranging mirroring works,
> > but I'm curious about what happens when an uncorrected memory error happens
> > on the a
On Fri, Jun 12, 2015 at 08:42:33AM +, Naoya Horiguchi wrote:
> 4?) I don't have the whole picture of how address ranging mirroring works,
> but I'm curious about what happens when an uncorrected memory error happens
> on the a mirror page. If HW/FW do some useful work invisible from kernel,
> p
On 2015/6/12 16:42, Naoya Horiguchi wrote:
> On Thu, Jun 04, 2015 at 08:54:22PM +0800, Xishi Qiu wrote:
>> Intel Xeon processor E7 v3 product family-based platforms introduces support
>> for partial memory mirroring called as 'Address Range Mirroring'. This
>> feature
>> allows BIOS to specify a
On Thu, Jun 04, 2015 at 08:54:22PM +0800, Xishi Qiu wrote:
> Intel Xeon processor E7 v3 product family-based platforms introduces support
> for partial memory mirroring called as 'Address Range Mirroring'. This feature
> allows BIOS to specify a subset of total available memory to be mirrored (and
Intel Xeon processor E7 v3 product family-based platforms introduces support
for partial memory mirroring called as 'Address Range Mirroring'. This feature
allows BIOS to specify a subset of total available memory to be mirrored (and
optionally also specify whether to mirror the range 0-4 GB). This
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