On Wed, Jun 01, 2016 at 03:45:45PM +0100, Will Deacon wrote:
> Hi David,
>
> On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> >
> > Here's a set of patches to provide kernel atomics and bitops implemented
> > with ISO C++11 atomic intrinsics. The second part of the set makes the
On Wed, Jun 01, 2016 at 03:45:45PM +0100, Will Deacon wrote:
> Hi David,
>
> On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> >
> > Here's a set of patches to provide kernel atomics and bitops implemented
> > with ISO C++11 atomic intrinsics. The second part of the set makes the
Hi David,
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
>
> Here's a set of patches to provide kernel atomics and bitops implemented
> with ISO C++11 atomic intrinsics. The second part of the set makes the x86
> arch use the implementation.
As you know, I'm really not a big
Hi David,
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
>
> Here's a set of patches to provide kernel atomics and bitops implemented
> with ISO C++11 atomic intrinsics. The second part of the set makes the x86
> arch use the implementation.
As you know, I'm really not a big
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
>
> Here's a set of patches to provide kernel atomics and bitops implemented
> with ISO C++11 atomic intrinsics. The second part of the set makes the x86
> arch use the implementation.
>
> Note that the x86 patches are very rough.
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
>
> Here's a set of patches to provide kernel atomics and bitops implemented
> with ISO C++11 atomic intrinsics. The second part of the set makes the x86
> arch use the implementation.
>
> Note that the x86 patches are very rough.
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> (1) We could weaken the kernel memory model to for the benefit of arches
> that have instructions that employ explicit acquire/release barriers -
> but that may cause data races to occur based on assumptions we've
>
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> (1) We could weaken the kernel memory model to for the benefit of arches
> that have instructions that employ explicit acquire/release barriers -
> but that may cause data races to occur based on assumptions we've
>
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> (3) I've added cmpxchg_return() and try_cmpxchg() to replace cmpxchg().
> I've also provided atomicX_t variants of these. These return the
> boolean return value from the __atomic_compare_exchange_n() function
>
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> (3) I've added cmpxchg_return() and try_cmpxchg() to replace cmpxchg().
> I've also provided atomicX_t variants of these. These return the
> boolean return value from the __atomic_compare_exchange_n() function
>
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> There are some advantages to using ISO C++11 atomics:
>
> (1) The compiler can make use of extra information, such as condition
> flags, that are tricky to get out of inline assembly in an efficient
> manner. This should
On Wed, May 18, 2016 at 04:10:37PM +0100, David Howells wrote:
> There are some advantages to using ISO C++11 atomics:
>
> (1) The compiler can make use of extra information, such as condition
> flags, that are tricky to get out of inline assembly in an efficient
> manner. This should
Here's a set of patches to provide kernel atomics and bitops implemented
with ISO C++11 atomic intrinsics. The second part of the set makes the x86
arch use the implementation.
Note that the x86 patches are very rough. It would need to be made
compile-time conditional in some way and the old
Here's a set of patches to provide kernel atomics and bitops implemented
with ISO C++11 atomic intrinsics. The second part of the set makes the x86
arch use the implementation.
Note that the x86 patches are very rough. It would need to be made
compile-time conditional in some way and the old
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