Venki Pallipadi <[EMAIL PROTECTED]> writes:
> Checking the manual for this. You are right, we had missed some steps here.
> Actually, manual says on MP, PAT MSR on all CPUs must be consistent (even when
> they are not really using it in their page tables.
> So, this will change the init and
Andi Kleen <[EMAIL PROTECTED]> writes:
>> I do know we need to use the low 4 pat mappings to avoid most of the PAT
>> errata issues.
>
> They don't really matter. These are all very old systems who have run
> fine for many years without PAT. It is no problem to let them
> continue to do so and
Andi Kleen [EMAIL PROTECTED] writes:
I do know we need to use the low 4 pat mappings to avoid most of the PAT
errata issues.
They don't really matter. These are all very old systems who have run
fine for many years without PAT. It is no problem to let them
continue to do so and just
Venki Pallipadi [EMAIL PROTECTED] writes:
Checking the manual for this. You are right, we had missed some steps here.
Actually, manual says on MP, PAT MSR on all CPUs must be consistent (even when
they are not really using it in their page tables.
So, this will change the init and shutdown
* Siddha, Suresh B <[EMAIL PROTECTED]> wrote:
> > Ok. I will send a separate patch fixing ioremap_nocache on x86.
>
> Appended the patch. x86 folks, please consider for x86 mm git tree.
> Thanks.
thanks, applied.
Ingo
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On Fri, Dec 14, 2007 at 01:10:39PM -0800, Siddha, Suresh B wrote:
> On Thu, Dec 13, 2007 at 09:23:26PM -0700, Eric W. Biederman wrote:
> > [EMAIL PROTECTED] (Eric W. Biederman) writes:
> > Ok. My analysis here was wrong. Currently pgprot_noncached and
> > ioremap_nocache are out of sync. With
On Thu, Dec 13, 2007 at 09:23:26PM -0700, Eric W. Biederman wrote:
> [EMAIL PROTECTED] (Eric W. Biederman) writes:
> Ok. My analysis here was wrong. Currently pgprot_noncached and
> ioremap_nocache are out of sync. With ioremap_nocache only specifying
> _PAGE_PCD and pgprot_noncached specifying
On Thu, Dec 13, 2007 at 08:48:45PM -0700, Eric W. Biederman wrote:
> > + pat = PAT(0,WB) | PAT(1,WT) | PAT(2,UC_MINUS) | PAT(3,WC) |
> > + PAT(4,WB) | PAT(5,WT) | PAT(6,UC_MINUS) | PAT(7,WC);
>
> I strongly object to this configuration.
>
> The caching modes of interest
Andi Kleen wrote:
I do know we need to use the low 4 pat mappings to avoid most of the PAT
errata issues.
They don't really matter. These are all very old systems who have run
fine for many years without PAT. It is no problem to let them
continue to do so and just disable PAT for them. So
On Fri, Dec 14, 2007 at 01:42:12AM +0100, Andi Kleen wrote:
> > +void __cpuinit pat_init(void)
> > +{
> > + /* Set PWT+PCD to Write-Combining. All other bits stay the same */
> > + if (cpu_has_pat) {
>
> All the old CPUs (PPro etc.) with known PAT bugs need to clear this flag
> now in their
> I do know we need to use the low 4 pat mappings to avoid most of the PAT
> errata issues.
They don't really matter. These are all very old systems who have run
fine for many years without PAT. It is no problem to let them
continue to do so and just disable PAT for them. So just clear pat bit
I do know we need to use the low 4 pat mappings to avoid most of the PAT
errata issues.
They don't really matter. These are all very old systems who have run
fine for many years without PAT. It is no problem to let them
continue to do so and just disable PAT for them. So just clear pat bit in
On Fri, Dec 14, 2007 at 01:42:12AM +0100, Andi Kleen wrote:
+void __cpuinit pat_init(void)
+{
+ /* Set PWT+PCD to Write-Combining. All other bits stay the same */
+ if (cpu_has_pat) {
All the old CPUs (PPro etc.) with known PAT bugs need to clear this flag
now in their CPU init
Andi Kleen wrote:
I do know we need to use the low 4 pat mappings to avoid most of the PAT
errata issues.
They don't really matter. These are all very old systems who have run
fine for many years without PAT. It is no problem to let them
continue to do so and just disable PAT for them. So
On Thu, Dec 13, 2007 at 09:23:26PM -0700, Eric W. Biederman wrote:
[EMAIL PROTECTED] (Eric W. Biederman) writes:
Ok. My analysis here was wrong. Currently pgprot_noncached and
ioremap_nocache are out of sync. With ioremap_nocache only specifying
_PAGE_PCD and pgprot_noncached specifying
On Thu, Dec 13, 2007 at 08:48:45PM -0700, Eric W. Biederman wrote:
+ pat = PAT(0,WB) | PAT(1,WT) | PAT(2,UC_MINUS) | PAT(3,WC) |
+ PAT(4,WB) | PAT(5,WT) | PAT(6,UC_MINUS) | PAT(7,WC);
I strongly object to this configuration.
The caching modes of interest are:
On Fri, Dec 14, 2007 at 01:10:39PM -0800, Siddha, Suresh B wrote:
On Thu, Dec 13, 2007 at 09:23:26PM -0700, Eric W. Biederman wrote:
[EMAIL PROTECTED] (Eric W. Biederman) writes:
Ok. My analysis here was wrong. Currently pgprot_noncached and
ioremap_nocache are out of sync. With
* Siddha, Suresh B [EMAIL PROTECTED] wrote:
Ok. I will send a separate patch fixing ioremap_nocache on x86.
Appended the patch. x86 folks, please consider for x86 mm git tree.
Thanks.
thanks, applied.
Ingo
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To unsubscribe from this list: send the line unsubscribe linux-kernel
[EMAIL PROTECTED] (Eric W. Biederman) writes:
> We should use:
>> +pat = PAT(0,WB) | PAT(1,WT) | PAT(2,WC) | PAT(3,UC) |
>> + PAT(4,WB) | PAT(5,WT) | PAT(6,WC) | PAT(7,UC);
>
> Changing the UC- which currently allows write-combining if the MTRRs specify
> it,
> to
[EMAIL PROTECTED] writes:
> Originally based on a patch from Eric Biederman, but heavily changed.
>
> Forward port of pat-base.patch to x86 tree, with a bug fix.
> Code was using 'PCD|PWT' i.e., PAT3 for WC mapping. So set the WC mapping at
> correct PAT fields PA3/PA7.
Well that wasn't from my
> +void __cpuinit pat_init(void)
> +{
> + /* Set PWT+PCD to Write-Combining. All other bits stay the same */
> + if (cpu_has_pat) {
All the old CPUs (PPro etc.) with known PAT bugs need to clear this flag
now in their CPU init functions. It is fine to be aggressive there
because these
Originally based on a patch from Eric Biederman, but heavily changed.
Forward port of pat-base.patch to x86 tree, with a bug fix.
Code was using 'PCD|PWT' i.e., PAT3 for WC mapping. So set the WC mapping at
correct PAT fields PA3/PA7.
TBD: KEXEC and other CPU offline paths may need
Originally based on a patch from Eric Biederman, but heavily changed.
Forward port of pat-base.patch to x86 tree, with a bug fix.
Code was using 'PCD|PWT' i.e., PAT3 for WC mapping. So set the WC mapping at
correct PAT fields PA3/PA7.
TBD: KEXEC and other CPU offline paths may need
+void __cpuinit pat_init(void)
+{
+ /* Set PWT+PCD to Write-Combining. All other bits stay the same */
+ if (cpu_has_pat) {
All the old CPUs (PPro etc.) with known PAT bugs need to clear this flag
now in their CPU init functions. It is fine to be aggressive there
because these old
[EMAIL PROTECTED] writes:
Originally based on a patch from Eric Biederman, but heavily changed.
Forward port of pat-base.patch to x86 tree, with a bug fix.
Code was using 'PCD|PWT' i.e., PAT3 for WC mapping. So set the WC mapping at
correct PAT fields PA3/PA7.
Well that wasn't from my
[EMAIL PROTECTED] (Eric W. Biederman) writes:
We should use:
+pat = PAT(0,WB) | PAT(1,WT) | PAT(2,WC) | PAT(3,UC) |
+ PAT(4,WB) | PAT(5,WT) | PAT(6,WC) | PAT(7,UC);
Changing the UC- which currently allows write-combining if the MTRRs specify
it,
to WC. This
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