Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-21 Thread Sam Ravnborg
Hi Mike. > Or, perhaps we only enable > the shared context ID feature on processors which have the ability to work > around the backwards compatibility feature. Start out like this, and then see if it is really needed with the older processors. This should keep the code logic simpler - which is

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-21 Thread Sam Ravnborg
On Sun, Dec 18, 2016 at 04:22:31PM -0800, Mike Kravetz wrote: > On 12/16/2016 11:45 PM, Sam Ravnborg wrote: > > Hi Mike > > > >> diff --git a/arch/sparc/kernel/fpu_traps.S b/arch/sparc/kernel/fpu_traps.S > >> index 336d275..f85a034 100644 > >> --- a/arch/sparc/kernel/fpu_traps.S > >> +++ b/arch/sp

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-20 Thread Mike Kravetz
On 12/20/2016 10:33 AM, David Miller wrote: > From: Mike Kravetz > Date: Sun, 18 Dec 2016 16:06:01 -0800 > >> Ok, let me try to find a way to eliminate these loads unless the application >> is using shared context. >> >> Part of the issue is a 'backwards compatibility' feature of the processor >>

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-20 Thread David Miller
From: Mike Kravetz Date: Sun, 18 Dec 2016 16:06:01 -0800 > Ok, let me try to find a way to eliminate these loads unless the application > is using shared context. > > Part of the issue is a 'backwards compatibility' feature of the processor > which loads/overwrites register 1 every time register

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-18 Thread Mike Kravetz
On 12/16/2016 11:45 PM, Sam Ravnborg wrote: > Hi Mike > >> diff --git a/arch/sparc/kernel/fpu_traps.S b/arch/sparc/kernel/fpu_traps.S >> index 336d275..f85a034 100644 >> --- a/arch/sparc/kernel/fpu_traps.S >> +++ b/arch/sparc/kernel/fpu_traps.S >> @@ -73,6 +73,16 @@ do_fpdis: >> ldxa

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-18 Thread Mike Kravetz
On 12/17/2016 07:14 PM, David Miller wrote: > From: Mike Kravetz > Date: Fri, 16 Dec 2016 10:35:27 -0800 > >> In current code, only context ID register 0 is set and used by the MMU. >> On sun4v platforms that support MMU shared context, there is an additional >> context ID register: specifically

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-17 Thread David Miller
From: Mike Kravetz Date: Fri, 16 Dec 2016 10:35:27 -0800 > In current code, only context ID register 0 is set and used by the MMU. > On sun4v platforms that support MMU shared context, there is an additional > context ID register: specifically context register 1. When searching > the TLB, the MM

Re: [RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-16 Thread Sam Ravnborg
Hi Mike > diff --git a/arch/sparc/kernel/fpu_traps.S b/arch/sparc/kernel/fpu_traps.S > index 336d275..f85a034 100644 > --- a/arch/sparc/kernel/fpu_traps.S > +++ b/arch/sparc/kernel/fpu_traps.S > @@ -73,6 +73,16 @@ do_fpdis: > ldxa[%g3] ASI_MMU, %g5 > .previous > > +661: n

[RFC PATCH 04/14] sparc64: load shared id into context register 1

2016-12-16 Thread Mike Kravetz
In current code, only context ID register 0 is set and used by the MMU. On sun4v platforms that support MMU shared context, there is an additional context ID register: specifically context register 1. When searching the TLB, the MMU will find a match if the virtual address matches and the ID conta